1. Field of the Invention
This invention relates generally to burn-in procedures for integrated circuit chip packages and, more particularly, to a method for controlling burn-in of integrated circuit chips to prevent damage to the chip by excessive heat build-up resulting from applied power during the burn-in procedure.
2. Background Information
In the manufacture of integrated circuit chips and integrated circuit chip devices or packages, one of the final procedures performed on the chip or chip package is final burn-in and testing. It is important to note that powers seen during burn-in are rapidly increasing over time. Increase in device power over time is attributed to increased static leakage current per device corresponding to CMOS technology advancement. This is a trend that follows technology. The burn-in and testing is generally done on a plurality of chips in chip packages mounted in a fixture. The burn-in procedure usually takes many hours and includes subjecting each of the chips or chip packages to relatively high voltages and temperatures. The high voltage results in high power levels during burn-in. The burn-in procedure is necessary in order to assure good quality chips; thus, relatively stringent or aggressive parameters are set for both the chip voltage delivered to each chip and the temperature environment encountered by each chip during burn-in.
Because of these very aggressive standards, it is necessary that they not be exceeded or damage likely will result to the chips. This is especially true of the temperature to which the chip is to be heated. For example, it is common for the test parameters of the chip to be set at 120Âxc2x0 C. plus or minus 5Âxc2x0 C. If during testing the temperature of the chip exceeds the maximum allowable temperature, i.e. about 125Âxc2x0 C. in this case, a relatively high likelihood of damage to the chip is the result, thus damaging a chip that would otherwise be a good and serviceable chip if tested within the temperature parameters set by the test. In some cases, the burn-in test equipment has over temperature and over voltage protection. However, even when these are present, and they actuate, this burn-in station is rendered non-functioning, and thus the chip at this station is not burned-in. This results in a lower equipment efficiency. Hence, it is desirable to have as many stations as possible operating.
One contributing factor to the temperature encountered by the chip during the test procedure is the thermal resistance between the chip and a heatsink used in the testing device. Thermal resistance between the chip and the heatsink can vary from test position to test position of the various chips or chip packages being tested in a single test fixture. There are many causes for this variation in thermal resistance at the interface between the heatsink and the chip. For example, differences in surface finish or flatness of the various heatsinks for each individual chip package can cause significant variation in thermal resistance; also, different surface finish or flatness of the back side of the chip which is in contact with the heatsink can also cause differences in the thermal resistance. Other causes of high thermal resistance include foreign bodies, such as dust or other particles at the interface. Moreover, different size I/C chip packages and heatsinks will have different thermal resistance at their interfaces. Too high a thermal resistance at the interface between the heatsink and the chip can result in thermal heating of the chip above allowable limits, thus destroying what might otherwise be a perfectly good chip. Therefore, it is desirable to provide a technique of preventing excessive heating of an I/C chip during burn-in.
According to the present invention, an improved method of burn-in of I/C chips is provided wherein at the beginning of the burn-in process, the thermal resistance between the heatsink and the chip is measured at reduced power (theoretically, the thermal resistance is independent of the power level), the maximum allowable thermal resistance between the chip and heatsink is calculated and compared to the actual thermal resistance of the interface. If the actual thermal resistance measured at the interface between the heatsink and the chip package is greater than the maximum allowable calculated thermal resistance, then the corrective action is initiated in order to prevent damage to the I/C chip during burn-in or increase efficient use of test sites.